1. Field of the Invention
The present invention relates to testing during the process of developing of computer system components. More specifically, the present invention relates to a method and an apparatus that selectively provides visibility and control over components within a programmable logic circuit for emulation purposes.
2. Related Art
Because of recent increases in speed and gate count for field programmable gate arrays (FPGAs), it is presently possible to move large cores from custom application specific integrated circuits (ASICs) into FPGAs. This potentially provides a powerful tool for debugging logic. The register transfer level (RTL) code for a large core from an ASIC can be loaded into a FPGA and can be tested within an operating computer system.
Unfortunately, this technique does not provide the same visibility and control that is present in a logic simulation program. Logic simulation programs typically allow different signals to be monitored and/or controlled during a simulation, which can be extremely useful in determining the cause of an error.
One disadvantage of logic simulation programs is that they are extremely slow. They operate many hundreds or thousands of times slower than the actual speed of the logic that is being simulated. Hence, logic simulation programs can only be used for a limited number of test cases. Otherwise, the simulation time becomes prohibitively long. Furthermore, logic simulation cannot be used to test a design within a computer system that is operating at full speed. Hence, it is not feasible to test real-time interactions with other components in a computer system using logic simulation.
What is needed is a system that provides visibility and control over memory elements within a design that is loaded into a programmable logic circuit during emulation of a logic circuit.
One embodiment of the present invention provides a system for selectively providing visibility and control over components within a programmable logic circuit during the process of emulating a logic circuit. The system operates by receiving a specifier for a memory element to be accessed during emulation of the logic circuit. This memory element resides within a design specifying logic to be programmed into the programmable logic circuit. Upon receiving the specifier, the system modifies the design so that the memory element is accessible through I/O pins on the programmable logic circuit, and then programs the modified design into the programmable logic circuit. Next, the design is tested by operating the programmable logic circuit and accessing the memory element.
In one embodiment of the present invention, the memory element includes a register.
In one embodiment of the present invention, the programmable logic circuit includes a field programmable gate array (FPGA).
In one embodiment of the present invention, modifying the design includes mapping the memory element into an address space of a bus that is coupled to the I/O pins. This allows the memory element to be accessed by a testing program.
In one embodiment of the present invention, accessing the memory element includes reading a value from the memory element and displaying the value.
In one embodiment of the present invention, accessing the memory element includes writing a value into the memory element.
In one embodiment of the present invention, the system migrates the design to an application specific integrated circuit (ASIC) if the testing indicates that the design functions properly within the programmable logic circuit.
In one embodiment of the present invention, the system includes receiving a specifier for a breakpoint condition within the programmable logic circuit. This specifier indicates when execution of the programmable logic circuit is to be stopped. In response to this break point specifier, the system modifies the design so that the programmable logic circuit is stopped when the breakpoint condition occurs. This may be accomplished by modifying the design so that a clock signal stops when the breakpoint condition occurs, or by modifying the design so that a state machine within the programmable logic circuit stops changing states when the breakpoint condition occurs.